1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a power semiconductor device employed in circuits for large power, which comprises a terminal structure to surround a device active region.
2. Description of the Related Art
A power semiconductor chip comprises a device active region that contains a source and a gate electrode of a transistor formed therein, and a terminal section that surrounds the device active region. The terminal section is formed to relieve an electric field at an end of the semiconductor device active region. A most typical configuration of the terminal section includes planar termination using guard rings as shown in FIG. 25. In this case, an electric field placed at the terminal section for the device active region can be extended toward the outside of the semiconductor chip.
When a higher rated voltage is employed, however, it is required to space the guard rings in layers at a certain interval. In a recent typical IGBT or MOSFET with a rated voltage of 600 V, it is required to space a plurality of guard rings with widths of 20-30 μm at an interval of several tens of μm. Accordingly, the terminal section has a width as large as several hundreds of μm, which increases the area of the terminal section, resulting in a problem associated with an increased area of the entire semiconductor element.
JP-A 2001-15744, also filed by the present applicant, proposes a semiconductor device having a trench formed in a depth extending from an upper layer to a floating doping layer in a terminal section of Super FET structure. This configuration is effective to prevent a breakdown voltage of the semiconductor device from lowering without increasing the area of the terminal section. In the semiconductor device disclosed in JP-A 2001-15744, however, the effect is exerted in elements having the floating doping layer and not sufficiently exerted in semiconductor elements having no floating doping layer.